A typical capacitor includes a lower electrode, an upper electrode and a dielectric film interposed therebetween. Since the capacitor accumulates charges, it has been used for data storage in semiconductor memory devices. One type of semiconductor memory device is DRAM (“dynamic random access memory”) which can form a unit cell having one transistor for inputting/outputting data and one capacitor for storing the data.
Unfortunately, with present trends toward high integration of semiconductor devices, the capacitance of semiconductor capacitors may continue to decrease. One technique which has been proposed to solve this problem is to use a dielectric film of a capacitor that has a higher dielectric value than oxide-nitride-oxide (ONO). However, the dielectric film can undesirably react on the lower electrode to deteriorate a capacitor characteristic (e.g., leakage current). In order to overcome the potential deterioration of the capacitor characteristic, a capacitor having a metal-insulator-metal (MIM) structure (hereinafter referred to as “MIM capacitor”) has been proposed. The MIM capacitor includes a lower electrode, an upper electrode, and a metal layer (particularly, noble metal layer) to reduce the capacitor leakage current. Further, the MIM capacitor may constitute the unit cell of a ferroelectric memory device. Similar to a DRAM unit cell, the unit cell of the ferroelectric memory includes one transistor and one capacitor. A difference therebetween is that the capacitor of the ferroelectric memory device has a dielectric film made of ferroelectric. Since the ferroelectric film has a polarization hysteresis characteristic, a capacitor using the ferroelectric film can retain its stored data even when its power supply is interrupted.
When fabricating a semiconductor device having the MIM capacitor, an oxidation barrier pattern is conventionally formed between a lower electrode and an underlying contact plug. During an annealing process for crystallizing a high-k dielectric film or a ferroelectric film, the lower electrode or the contact plug may be oxidized to increase contact resistance. The oxidation barrier pattern can reduce the increase of the annealing-induced contact resistance.
A first conventional method for forming a lower electrode of a conventional MIM capacitor is described below with reference to FIG. 1 and FIG. 2. Another conventional method for forming a lower electrode and an oxidation barrier pattern of a conventional MIM capacitor is described below with reference to FIG. 3.
Referring to FIG. 1 and FIG. 2, a lower interlayer dielectric 2 is formed on a semiconductor substrate 1. Buried contact plugs 3 are formed through the lower interlayer dielectric 2 to connect to a predetermined region of the semiconductor substrate 1. An oxidation barrier pattern 4 is formed over a top surface of the buried contact plug 3. An upper interlayer dielectric 5 is formed on an entire surface of a semiconductor substrate including the oxidation barrier pattern 4. The upper interlayer dielectric 5 is patterned to form a lower electrode recess 6 exposing a predetermined region of the oxidation barrier pattern 4. A lower electrode layer 7 is formed on an entire surface of the semiconductor substrate 1 including an inside of the lower electrode recess 6. A sacrificial insulating layer 8 is formed on the lower electrode layer 7 to fill the lower electrode recess 6. The lower electrode layer 7 is made of metal. As shown in FIG. 2, the sacrificial insulating layer 8 and the lower electrode layer 7 are planarized down to a top surface of the upper interlayer dielectric 5 to form a lower electrode 7a and a sacrificial insulating pattern 8a which are sequentially stacked in the lower electrode recess 6.
In view of a design constraint, the oxidation barrier pattern 4 is minimally spaced apart from an adjacent oxidation barrier pattern 4. The lower electrode recess 6 may not entirely expose the top surface of the oxidation barrier pattern 4 because of an alignment margin 10 between the lower electrode recess 6 and the oxidation barrier pattern 4. That is, the top surface of the oxidation barrier pattern 4 has an area which is obtained by adding an area corresponding to the bottom surface of the lower electrode 7a to the area corresponding to the alignment margin(s) 10 of the oxidation barrier pattern 4. Accordingly, the surface area of the lower electrode 7a may be smaller than that of a lower electrode formed without the oxidation barrier pattern 4.
Referring to FIG. 3, the buried contact plug 3 is formed through the lower interlayer dielectric 2 to the semiconductor substrate 1. The buried contact plug 3 is connected to a predetermined region of the semiconductor substrate 1. The upper interlayer dielectric 5 is formed on an entire surface of a semiconductor substrate 1 including the buried contact plug 3. The upper interlayer dielectric layer 5 is patterned to form a lower electrode recess 6 exposing a top surface of the interlayer dielectric 5. An oxidation barrier layer (not shown) and a lower electrode layer (not shown) are sequentially formed on an entire surface of a semiconductor substrate 1 including an inside of the lower electrode recess 6. A sacrificial insulating layer (not shown) is formed on the lower electrode layer to fill the lower electrode recess 6. The sacrificial insulating layer, the lower electrode layer, and the oxidation barrier layer are sequentially planarized down to a top surface of the interlayer dielectric 5 to form an oxidation barrier pattern 4a, the lower electrode 7a, and a sacrificial insulating pattern 8a which are sequentially stacked in the lower electrode recess 6.
The oxidation barrier pattern 4a is also formed on a bottom side and sidewalls of the lower electrode 7a. In this case, a surface area of the lower electrode 7a is smaller than that of a lower electrode without the oxidation barrier pattern 4b. This is because the oxidation barrier layer 4a is formed on the sidewalls of the lower electrode 7a to thereby reduce the size of the lower electrode 7a. 